The invention relates to high voltage tolerant thin film transistors. Table 1 provides a list of symbols used in this document and their meanings.
TABLE 1 ______________________________________ Useful Definitions ______________________________________ .ANG. Angstrom cm centimeter I.sub.D drain current keV kilo-electron volts MeV mega-electron volts v volt V.sub.D drain voltage V.sub.th transistor threshold voltage .OMEGA./.quadrature. ohms per square .mu.m micrometer ______________________________________
Semiconductors fabricated using complementary metal oxide semiconductor (CMOS) technology use polysilicon (Si, also referred to as polycrystaline or amorphous silicon) to form transistor gate structures. Early CMOS processes used polysilicon heavily doped with n-type impurities (n+) for both n-channel (NMOS) and p-channel (PMOS) transistor gates. In these technologies, PMOS transistor channel regions were counter doped with p-type impurities to achieve desired PMOS device threshold voltages.
Many recent CMOS technologies use what is referred to as a dual work function polysilicon (poly) process. As shown in FIG. 1A, a dual work function poly process begins by forming a layer of undoped polysilicon 100 over a substrate 102 that has previously had field regions 104 and active regions 106 defined by field oxide 108. Once formed, see FIG. 1B, polysilicon 100 is patterned and doped to provide n+ regions 110 (for NMOS device 112 gates) and p+ regions 114 (for PMOS device 116 gates). The added complexity of the dual work function process (over one-type polysilicon procedures) is offset by the ability to independently optimize both NMOS 112 and PMOS 116 devices.
Referring to FIG. 2A, at the time that polysilicon region 110 is doped to form a NMOS transistor gate, a region 200 is also n+ doped. Region 200 will become the lower plate of a polysilicon-polysilicon (poly--poly) capacitor.
Referring now to FIGS. 2B and 2C, after doping polysilicon 100, a layer of dielectric material 202 is laid down over region 200. Materials commonly used for dielectric material 202 include silicon dioxide (SiO.sub.2), oxide-nitride-oxide or ONO (SiO.sub.2 --Si.sub.3 N.sub.4 --SiO.sub.2), tetraethyl orthosilicate (TEOS), and silicon nitride (Si.sub.3 N.sub.4). A second n+ doped layer of polysilicon 204 is formed over dielectric 202 to provide the capacitor's top plate. A poly--poly capacitor (comprising lower plate n+ polysilicon 200, dielectric 202, and top plate n+ polysilicon 204) may be used for pole-splitting, amplifier compensation, charge redistribution, or as an element in a filter or attenuator.
Advances in CMOS fabrication techniques, especially those including a dual work function poly process, allow the design and manufacture of integrated circuits having very high device packing densities. One consequence of increasing transistor densities is that device operating voltages are generally getting lower. Whereas older transistor-transistor logic (TTL) circuits were designed to operate at approximately 5v, newer circuits such as memory devices and central processing units are being designed to operate at 3.3v, 2.5v, and 1.8v.
These new low voltage devices are more susceptible to damage from high voltage signals than prior devices. For example, an integrated circuit implemented using 1.8v technology can be damaged when exposed to a high voltage signal, e.g., a signal of approximately 6v and above. It would be beneficial to integrate both low voltage and high voltage devices into a single integrated circuit on a single substrate. The combined integration of low and high voltage devices would make possible the design and manufacture of complete functional circuits; circuits having both logic and direct input-output control capability.